1. Technical Field
The present invention pertains to memory devices. In particular, the present invention pertains to externally controlling a self-refresh oscillator within a memory device during a test mode to enable measurement of various memory operating characteristics.
2. Discussion of the Related Art
Memory devices are utilized to store information for various applications. A commonly utilized memory device includes a dynamic random access memory (DRAM). These types of memory devices store information in memory cell arrays that are configured in a matrix of intersecting rows and columns. The rows are commonly referred to as word lines. Each memory cell generally includes a storage capacitor to hold a charge and a transistor to access the charge of the capacitor. The charge may be a high or low voltage potential (referred to as a data bit), thereby providing the memory cell with two logic states.
The memory cells of the DRAM must be refreshed periodically due to leakages within the capacitors storing the charges (or bits). The refresh operation may be performed either by a memory controller issuing an auto-refresh (or “CBR”) command, or by the memory in a self-refresh mode. During the self-refresh mode, a self-refresh pulse generator or oscillator within a memory self-refresh unit generates self-refresh pulses to enable each memory cell to be refreshed according to a desired specification. Further, the memory includes a power or generator system to generate appropriate internal voltages for memory operation. For low power memory designs (e.g., CellularRAMs, MobileRAMs, etc.), a portion of the power or generator system is clocked to permit that system to be enabled a certain percentage (e.g., 10%, etc.) of the time during a self-refresh mode in order to conserve current. The clocked standby mode (e.g., mode or time interval in which the generator system is idle) for the generator system is controlled by control signals or pulses received from the self-refresh unit based on the generated self-refresh pulses.
For test purposes, full control over generation of the self-refresh pulses and the clocked standby mode is highly desirable. Accordingly, some flexibility exists in adjusting (e.g., increasing or reducing) clocked standby mode pulses (e.g., in frequency, pulse width, etc.) by a certain factor. Alternatively, generation of the self-refresh pulses may be controlled by changing a constant current provided to the self-refresh oscillator within the self-refresh unit, or by altering capacitances of capacitors within that oscillator. For example, generation of the self-refresh pulses may be varied from a very high frequency to a very low frequency for cell charge retention tests. These techniques enable adjustment of the clocked standby period by specific factors (e.g., one-half, one, two, four, etc.).
The techniques described above suffer from several disadvantages. In particular, there is no manner providing full control of the clocked standby mode with respect to testing. Although the techniques enable variation of the period of the clocked standby mode by specific factors, there is no manner providing utilization of intermediate factor values or extending the clocked standby mode period for long durations (e.g., eternity). This latter capability is needed to ascertain the limits of each voltage generated by the generator system in the clocked standby mode (e.g., thereby optimizing stability and robustness with conservation of current).
In addition, there is no manner of linking or synchronizing an external command sequence or other interface (e.g., self-refresh entry and exit commands from an external test unit) with the internal self-refresh oscillator. In other words, the self-refresh oscillator operates independently or in an asynchronous manner with respect to the external command sequence or interface. This occurs even in the event of adjustment of the clocked standby mode period by the above-described techniques. The linking capability is needed to test various worst case conditions, such as when a self-refresh exit command is received just before the next clocked standby mode. In this worst case condition, the internal voltages for the memory are generated by the power or generator system in response to a standby mode pulse enabling the system for a portion of the self-refresh interval. However, the generated voltages decrease in potential during the standby mode when the generator system is idle. Thus, the internal voltages basically continually increase (e.g., generation by the power system during enablement) and decrease (e.g., standby or idle mode of the power system) during memory operation, thereby forming a ripple type pattern. The worst case condition of exiting a self-refresh mode just prior to a standby mode pulse represents the maximum reduction in potential of the internal voltages (e.g., after a standby mode and prior to power system enablement), where the voltages are typically furthest from corresponding target voltages. The linking capability is further needed to test other worst case conditions relating to certain interface specification parameters. For example, timings for various memory products (e.g., Pseudo-SRAM, Cellular RAM, etc.) are based on worst case conditions where an internal refresh event occurs at a certain time relative to external commands applied to the chip. Another example includes a timing specification for DRAMs with respect to an exit from self-refresh. Although tests may be conducted for several hours to ascertain values for each possible time difference between internally clocked standby mode pulses and externally generated self-refresh exit or other commands, these tests rely on chance to capture the worst case conditions where there is extremely low probability that the values for the worst case conditions (e.g., receiving a self-refresh exit command just before a clocked standby pulse, etc.) may be obtained in a reasonable time period.